Simulation system for testing a radar system

ABSTRACT

A simulation system for use in testing a radar system comprises a coarse delay module, a fine delay module, and a doppler shift module. The coarse delay module is configured to receive a first stream of digital data samples that are sampled from a radar signal at a sample time period or a second stream of digital data samples that are processed by another simulation system component and delay the digital data samples by a selectable first delay time that is greater than or equal to the sample time period. The fine delay module is configured to receive the digital data samples and filter the digital data samples to represent delay by a selectable second delay time that is less than the sample time period. The doppler shift module is configured to receive the digital data samples and adjust a value of a frequency content of the fine delayed samples.

STATEMENT REGARDING FEDERALLY-SPONSORED RESEARCH OR DEVELOPMENT

This invention was made with Government support under Contract No.:DE-NA00002839 awarded by the United States Department of Energy/NationalNuclear Security Administration. The Government has certain rights inthe invention.

RELATED APPLICATION

The current patent application is a continuation patent applicationwhich claims priority benefit, with regard to all common subject matter,of earlier-filed U.S. Pat. Application Ser. No. 16/822,197, titled “ASIMULATION SYSTEM FOR TESTING A RADAR SYSTEM”, and filed Mar. 18, 2020.The listed earlier-filed patent application is hereby incorporated byreference, in its entirety, into the current patent application.

FIELD OF THE INVENTION

Embodiments of the current invention relate to systems that simulatetargets to test radar systems.

DESCRIPTION OF THE RELATED ART

Radio detection and ranging (radar) systems transmit radio frequencywireless signals, also known as radio waves, into a region or space andreceive reflections of the radio waves. The radio waves are transmittedand received by one or more antennas. The reflections are created by theradio waves bouncing off, or reflecting from, objects (also known as“targets”) in the path of the radio waves. The objects may includeaircraft, ships, spacecraft, guided missiles, motor vehicles, weatherformations, terrain, and the like. The characteristics of thereflections, such as time delay between transmission and reception,frequency shift of the radio waves, angle of arrival, and so forth, areanalyzed by the radar system to determine a range from the radar source,an angle or bearing from the source, and/or a velocity of the objects.To verify the operation of a radar system, it needs to be tested. Astraightforward approach to testing may involve placing objects at knowndistances or locations from the radar source and operating the radarsystem to verify that it detects the objects in the correct location.However, to fully test the radar system, different types of objects,such as aircraft, vehicles, etc., would need to be used. The objectswould need to be placed at a variety of distances and angles from theradar source. Furthermore, some objects would need to be stationary,while others should be moving. Thorough testing of the radar system withthis approach would be time consuming and costly.

SUMMARY OF THE INVENTION

Embodiments of the current invention solve the above-mentioned problemsand provide a simulation system to simulate objects, or targets, fortesting a radar system. Instead of receiving the radio waves from theradar system and reflecting them back to simulate objects at variouslocations, the simulation system receives from the radar system a firstelectronic signal that would normally be provided to one or moreantennas that transmit the radio waves. The simulation system alsoprovides to the radar system a second electronic signal that wouldnormally be generated by one or more antennas as a result of receivingreflections. The simulation system includes components, described inmore detail below, that can delay the electronic signal from the radarsystem in order to simulate objects at a variety of ranges, objects thatare stationary, wobbling, scintillating, or moving, and objects that aremoving toward or away from the radar source. Since the simulation systemdoes not involve physical objects, it can test the radar system quicklyand cost effectively, and provide a repeatable, deterministic, and highquality simulation.

An exemplary simulation system broadly comprises a coarse delay module,a fine delay module, and a doppler shift module. The coarse delay moduleis configured to receive either a first stream of digital data samplesthat are sampled from a radar signal at a sample time period or a secondstream of digital data samples that are processed by another simulationsystem component, delay the digital data samples by a selectable firstdelay time that is greater than or equal to the sample time period, andoutput coarse delayed samples. The fine delay module is configured toreceive either the first stream of digital data samples or the secondstream of digital data samples, filter the digital data samples torepresent delay by a selectable second delay time that is less than thesample time period, and output fine delayed samples. The doppler shiftmodule is configured to receive either the first stream of digital datasamples or the second stream of digital data samples, adjust a value ofone or more frequency components of the digital data samples, and outputdoppler shifted samples.

Another embodiment of the current invention provides a simulation systemfor use in testing a radar system comprising a coarse delay module, afine delay module, and a doppler shift module. The coarse delay moduleis configured to receive either a first stream of digital data samplesthat are sampled from a radar signal at a sample time period or a secondstream of digital data samples that are processed by another simulationsystem component, delay the digital data samples by a selectable firstdelay time that is greater than or equal to the sample time period, andoutput coarse delayed samples. The coarse delay module includes a memoryelement and a memory controller. The memory element is configured toreceive the digital data samples and store them, with each digital datasample being stored in a different one of a plurality of memorylocations. The memory element is further configured to transmit thedigital data samples.

The fine delay module is configured to receive either the first streamof digital data samples or the second stream of digital data samples,filter the digital data samples to represent delay by a selectablesecond delay time that is less than the sample time period, and outputfine delayed samples. The fine delay module includes a fractional delayfilter and a fractional delay controller. The fractional delay filterincludes a plurality of computational stages configured to perform aninterpolation calculation to determine values of the digital datasamples at the second delay time. The fractional delay controller isconfigured to control the operation of the fractional delay filter bysetting parameters of the computational stages.

The doppler shift module is configured to receive either the firststream of digital data samples or the second stream of digital datasamples, adjust a value of one or more frequency components of thedigital data samples, and output doppler shifted samples.

Yet another embodiment of the current invention provides a simulationsystem for use in testing a radar system comprising a doppler shiftmodule, a fine delay module, and a coarse delay module. The fine delaymodule is configured to receive either a first stream of digital datasamples that are sampled from a radar signal at a sample time period ora second stream of digital data samples that are processed by anothersimulation system component. The fine delay module includes a variabletime delay unit and a fractional delay filter. The variable time delayunit is configured to receive the digital data samples, delay them by avariable time period, and output variable time delayed samples. Thefractional delay filter is configured to receive the variable timedelayed samples, filter the variable time delayed samples to representdelay by a selectable first delay time that is less than the sample timeperiod, and output fine delayed samples. The doppler shift module isconfigured to receive either the first stream of digital data samples orthe second stream of digital data samples, adjust a value of one or morefrequency components of the digital data samples, and output dopplershifted samples. The coarse delay module configured to receive eitherthe first stream of digital data samples or the second stream of digitaldata samples, delay the digital data samples by a selectable seconddelay time that is greater than or equal to the sample time period, andoutput coarse delayed samples.

This summary is provided to introduce a selection of concepts in asimplified form that are further described below in the detaileddescription. This summary is not intended to identify key features oressential features of the claimed subject matter, nor is it intended tobe used to limit the scope of the claimed subject matter. Other aspectsand advantages of the current invention will be apparent from thefollowing detailed description of the embodiments and the accompanyingdrawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

Embodiments of the current invention are described in detail below withreference to the attached drawing figures, wherein:

FIG. 1 is a schematic block diagram of a simulation system, constructedin accordance with various embodiments of the current invention, fortesting a radar system;

FIG. 2 is a schematic block diagram of a fractional delay filter of thesimulation system;

FIG. 3 is a plot of power versus frequency illustrating an output of aprior art simulation system, the plot showing the presence a number ofobjects when there should be only one object;

FIG. 4 is a plot of power versus frequency illustrating an output of thesimulation system of the current invention, the plot correctly showingthe presence of one object; and

FIG. 5 is a schematic block diagram of a second embodiment of thesimulation system.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The drawing figures do not limit the current invention to the specificembodiments disclosed and described herein. The drawings are notnecessarily to scale, emphasis instead being placed upon clearlyillustrating the principles of the invention.

The following detailed description of the technology references theaccompanying drawings that illustrate specific embodiments in which thetechnology can be practiced. The embodiments are intended to describeaspects of the technology in sufficient detail to enable those skilledin the art to practice the technology. Other embodiments can be utilizedand changes can be made without departing from the scope of the currentinvention. The following detailed description is, therefore, not to betaken in a limiting sense. The scope of the current invention is definedonly by the appended claims, along with the full scope of equivalents towhich such claims are entitled.

A simulation system 10, constructed in accordance with variousembodiments of the current invention, for simulating targets, or objectsof interest, while testing a radar system 12 is shown in FIG. 1 . Thesimulation system 10 may interface or communicate with intermediateelectronic circuitry including a down conversion circuit 14, an analogto digital converter 16, a digital to analog converter 18, an upconversion circuit 20, and an external controller 22.

The radar system 12 is a radio and ranging (RADAR) system that may beutilized to observe, identify, or track targets or objects of interestwhich are moving or stationary. The radar system 12 normally outputsradio frequency (RF) signals that are transmitted wirelessly via one ormultiple antennas (not shown in FIG. 1 ) and known as radar beams. Theradar system 12 also receives reflections of the beams that have bouncedoff or reflected from objects within the path of the radar beams, i.e.,the targets. The radar system 12 processes the received reflected radarbeams in order to determine the positions and velocities of the targets.However, to simplify the setup for testing the radar system 12, theradar system 12 may be configured without its antennas as shown in FIG.1 . In this configuration, the radar system 12 outputs RF electronicsignals that are not ever transmitted wirelessly. The radar system 12also receives RF electronic signals, such as a radar input signal, whichrepresents reflections of the radar beams.

The down conversion circuit 14 generally receives an electronic signalthat includes one or more frequency components and converts allfrequency components of the electronic signal from a higher frequencyvalue to a lower frequency value. The down conversion circuit 14 mayinclude, or be formed from, electronic components and circuits, such astunable oscillators, mixers, filters, detectors, amplifiers, and thelike. The down conversion circuit 14 receives the radar output signalfrom the radar system 12 and converts the radar output signal from ahigher frequency value to a lower frequency value. The down conversioncircuit 14 outputs a down-converted signal which includes the lowerfrequency component value.

The analog to digital converter (ADC) 16 generally converts an analogelectronic signal to a sequence of sampled digital values. The ADC 16may utilize, or implement, any one of a plurality of conversionarchitectures, such as direct conversion, successive approximation, rampcompare, Wilkinson, integrating, etc. The ADC 16 receives thedown-converted signal from the down conversion circuit 14, samples it ata sample frequency or rate whose inverse is a sample period, and outputsa stream of digital samples, with each sample having a value equal to,or corresponding to, a value of the electric voltage, or otherelectrical characteristic, of the down-converted signal when it wassampled.

The digital to analog converter (DAC) 18 generally converts a stream ofdigital values into an analog electronic signal whose waveform or shapeis determined by the digital values. The DAC 18 may utilize, orimplement, any one of a plurality of conversion architectures, such aspulse-width modulation, oversampling, interpolating, delta-sigma, binaryweighted, R-2R ladder, etc. The DAC 18 receives a simulation signal fromthe simulation system 10 and converts it to an analog intermediatefrequency signal.

The up conversion circuit 20 generally receives an electronic signalthat includes one or more frequency components and converts allfrequency components of the electronic signal from a lower frequencyvalue to a higher frequency value. The up conversion circuit 20 mayinclude, or be formed from, electronic components and circuits, such astunable oscillators, mixers, filters, detectors, amplifiers, and thelike. The up conversion circuit 20 receives the intermediate frequencysignal from the DAC 18 and converts the intermediate frequency signalfrom a lower frequency value to a higher frequency value. The upconversion circuit 20 outputs an up-converted signal which includes thehigher frequency component value.

The external controller 22 generally controls the overall operation ofthe simulation system 10 and monitors its performance. The externalcontroller 22 may be embodied by an embedded microcontroller or acomputer, such as a workstation computer, a desktop computer, a laptopcomputer, a tablet computer, and so forth. Utilizing a software program,the external controller 22 may automate testing or schedule one or moretests for the simulation system 10 to execute. Accordingly, the externalcontroller 22 may determine, or establish, the configuration orparameters for each test. The parameters may include a number of targetsto simulate, whether each target is stationary or moving, a velocity ofa moving target, and the like. Furthermore, based on feedback from theradar system 12, the external controller 22 may adjust the parameters ofthe tests or may schedule additional tests. In addition, the results ofeach test may be stored in, and evaluated by, the external controller22.

The simulation system 10 may broadly comprise an external configurationblock 24, a clock generator 26, a memory element 28, a memory controller30, a fractional delay filter 32, a fractional delay controller 34, asingle sideband modulator 36, and a control processor 38. The simulationsystem 10 may be implemented in a field programmable gate array (FPGA)or an application specific integrated circuit (ASIC), and thus thefunctions of the simulation system 10 may be executed in hardware,software, firmware, or combinations thereof. Portions of the simulationsystem 10 may be formed by the execution of code from a hardwaredescription language. Furthermore, the simulation system 10 may includememory or data storage that constitutes or embodies a non-transitory“computer-readable medium” capable of storing functional instructions,code, code statements, code segments, software, firmware, programs,applications, apps, services, daemons, or the like.

The external configuration block 24 generally acts as an interfacebetween the control processor 38, or the simulation system 10 ingeneral, and the external controller 22. The external configurationblock 24 may include electronic circuitry and/or software programming toperform logic processing and decision making. The external configurationblock 24 may send and receive commands, control signals, and/or datafrom the external controller 22. The external configuration block 24 mayalso send and receive commands, control signals, and/or data from thecontrol processor 38. In addition, the external configuration block 24may receive feedback in the form of commands, control signals, and/ordata from the radar system 12, typically during testing. The externalconfiguration block 24 may forward the feedback to both the externalcontroller 22 and the control processor 38.

The clock generator 26 generates a clock or timing signal to providesynchronous operation of the simulation system 10. The clock generator26 may include crystals, oscillators, square-wave generators, or thelike, or combinations thereof. The clock signal is periodic, typically asquare wave, and is generated with a clock frequency, whose inverse is aclock period or clock cycle. The clock signal is communicated to andreceived by the other components of the simulation system 10.

The memory element 28 stores the digital samples of the radar outputelectronic signal from the ADC 16, referred to hereinafter as “digitalsamples”, and may be embodied by devices or components that store datain general, and digital or binary data in particular, and may includeexemplary electronic hardware data storage devices or components such asrandom-access memory (RAM), i.e., static RAM (SRAM) or dynamic RAM(DRAM), or the like. The storage devices typically include a pluralityof storage locations (or addresses), wherein each storage location iscapable of storing a multibit data word (such as a digital sample of theradar output signal). The memory element 28 may also be formed from asequence of storage registers, such as shift registers, first-in,first-out (FIFO) structures, etc. The memory element 28 may furtherinclude at least one write memory pointer which stores the currentlocation or register in which digital samples have been written orstored. The memory element 28 may also include at least one read memorypointer which stores the current location or register in which digitalsamples have been read. The memory element 28 receives the stream ofdigital samples from the ADC 16. The samples are stored in, or writtento, the storage locations or registers, as determined by the writememory pointer, which are typically successive locations within thememory element 28. After a period of time determined by, or varyingaccording to, the parameters of the test that is being run, the digitalsamples are read from, or shifted out of, the storage locations orregisters, as determined by the read memory pointer.

The memory controller 30 generally controls the flow of data samplesinto and out of the memory element 28. The memory controller 30 may beformed from controller and/or processor electronic circuitry, such as afinite state machine (FSM), or the like, and may include additionallogic circuitry. Alternatively, the memory controller 30 may beimplemented as a software program or application. Based on commands,control signals, and/or data from the control processor 38, the memorycontroller 30 may set the values of the write and read memory pointersof the memory element 28 to control which storage locations or registershave samples written to them and which storage locations or registershave samples read from them. Thus, for each data sample, the memorycontroller 30 stores the sample in a memory location, waits for anamount of time, and then has the sample read from the memory locationand communicated to the next component. By controlling the amount oftime that each data sample is stored in a memory location, the memorycontroller 30 is controlling the amount of delay time that the memoryelement 28 introduces to the digital samples.

The memory element 28 and the memory controller 30 may form a coarsedelay module 40 which provides lower resolution control of the delay ofthe digital samples. That is, the coarse delay module 40 may delay thedata samples by relatively larger delay times, or times that are greaterthan or equal to the sample time period, which is “coarse delay”.

The fractional delay filter 32 generally provides the ability to filterthe digital samples to simulate or approximate delaying the digitalsamples by a fractional amount of the sample time period, which may alsobe known as the “unit delay”. This is akin to resampling thedown-converted signal at an offset from the time periods at which thedigital samples are created. For example, if the digital samples areprovided at a rate of 1 gigahertz (GHz), or 1 giga samples per second,then the sample time period would be 1 nanosecond (ns). This samplingrate yields a first digital sample at a time of 1 ns, a second digitalsample at a time of 2 ns, a third digital sample at a time of 3 ns, andso forth. Resampling at an offset would determine a value of the digitalsamples at times in between the known values, such as determiningdigital sample values at times of, for example, 1.5 ns, 2.5 ns, 3.5 ns,and so forth.

Since the fractional delay filter 32 cannot actually resample thedown-converted signal to obtain digital sample values at fractional,offset amounts of the sample time period, i.e., fractional delay times,the fractional delay filter 32 performs an interpolation calculation todetermine or approximate the digital sample values at fractional delaytimes. In various embodiments, the fractional delay filter 32 mayperform a Lagrange interpolation on the digital sample values todetermine or approximate their values at fractional delay times.

An exemplary fractional delay filter 32 includes a Farrow structuredfractional delay filter as shown in FIG. 2 and described in more detailin U.S. Pat. Application Serial No.: 16/985,884, entitled “FRACTIONALDELAY FILTER FOR A DIGITAL SIGNAL PROCESSING SYSTEM”, and filed Aug. 5,2020, which is hereby incorporated by reference in its entirety into thecurrent patent application. The fractional delay filter 32 includes aplurality of stages of computational blocks 42 and a standalone filterblock 44. Each computational block 42 includes a first input 46, asecond input 48, a filter block 50, a coefficient block 52, an adder 54,and an output 56. The fractional delay filter 32 can include N stages ofcomputational blocks 42 and one standalone filter block 44.

The first input 46 receives the digital sample from the memory element28 at a rate of one digital sample per clock cycle. The second input 48receives the output from an adjacent stage, which may be a successivestage, of computational block 42. The filter block 50, denoted asC_(n)(z), with n having a value ranging from 0 to N-1, may beimplemented as an Nth order finite impulse response (FIR) filter,wherein each FIR filter may have a plurality of filter stages, and eachfilter stage may require one or more coefficient values. The filterblock 50 receives its input from the first input 46, and outputs afiltered sample. The coefficient block 52 performs a multiplicationfunction wherein an input of the coefficient block 52 is multiplied by acoefficient with a selectable value of D. The input of the coefficientblock 52 is the second input 48, and the output is a coefficientproduct. The adder 54 adds the coefficient product and the filteredsample and outputs the sum of the two, which is the output 56 of thecomputational block 42.

The standalone filter block 44, which is the same in structure andfunction as the other filter blocks 50, also receives the digital samplefrom the memory element 28 as its input. The output of the standalonefilter block 44 is communicated to the second input 48 of the last stage(N-1) of the computational blocks 42.

Furthermore, the output 56 of the first stage (0) of the computationalblocks 42 is the filtered digital sample output of the fractional delayfilter 32.

A number of stages N, the filter block 50 (FIR) coefficients, and avalue of D can be chosen and adjusted to meet various designconstraints. In some situations, such as simulating a stationary target,the values of N, the filter block 50 coefficients, and D may be chosento provide no fractional delay.

The fractional delay controller 34 generally controls the operation ofthe fractional delay filter 32. The fractional delay controller 34 maybe formed from controller and/or processor electronic circuitry, such asan FSM, or the like, and may include additional logic circuitry.Alternatively, the fractional delay controller 34 may be implemented asa software or firmware program or application. Based on commands,control signals, and/or data from the control processor 38, thefractional delay controller 34 may set the number of stages N, thevalues of the coefficients for each filter block 50, and the value ofthe coefficient D.

The fractional delay filter 32 and the fractional delay controller 34may form a fine delay module 58 which provides higher resolution controlof the delay of the digital samples. That is, the fine delay module 58may filter the digital samples to represent a delay by relativelysmaller delay times, or times that are less than, or a fraction of, thesample time period, which is “fine delay”.

The single sideband modulator 36 generally adjusts values of a frequencycontent of the digital samples and may form a Doppler shift module 60.The single sideband modulator 36 may be formed from electronic circuitrysuch as oscillators, mixers, filters, and the like, or combinationsthereof. Alternatively, the single sideband modulator 36 may beimplemented as a software or firmware program or application. The singlesideband modulator 36 receives the digital samples from the fractionaldelay filter 32. The data of the digital samples may include a pluralityof frequency components which makes up the frequency content of thedigital samples. That is, f_(digital) _(samples) = [f₁, f₂, ..., f_(n)].

The single sideband modulator 36 may selectively or optionally adjust avalue of one of more frequency components of the digital samples byeither increasing the value or decreasing the value. The single sidebandmodulator 36 may receive commands, control signals, and/or data from thecontrol processor 38 to adjust the frequency components and an amount toadjust. For example, the frequency components of the digital samples mayhave initial values when the digital samples enter the single sidebandmodulator 36. If the single sideband modulator 36 receives commands,control signals, and/or data to adjust the frequency content, then thesingle sideband modulator 36 may process the digital samples to have ashifted frequency value for each frequency component that is greaterthan or less than the initial frequency value by an amount delta Δ. Thatis: f_(1shifted) = f_(1initial) +/- Δ, f_(2shifted) = f_(2initial) +/-Δ, ..., f_(nshifted) = f_(ninitial) +/- Δ. The single sideband modulator36 may shift all of the frequency components, or it may shift a portionthereof. In situations where no Doppler shift is required, then thesingle sideband modulator 36 may simply pass through the digital sampleswith no modification.

FIG. 1 shows an exemplary flow that the digital samples follow from theADC 16 to the coarse delay module 40, the fine delay module 58, and thento the Doppler shift module 60. In theory and in practice, the modules40, 58, 60 could be arranged in any sequence and the simulation system10 would still produce the same output.

The control processor 38 generally controls the operation of, and flowof digital samples through, the memory element 28, the fractional delayfilter 32, and the single sideband modulator 36. The control processor38 may be formed from controller and/or processor electronic circuitry,such as an FSM, or the like, and may include additional logic circuitry.Alternatively, the control processor 38 may be implemented as a softwareprogram or application. The control processor 38 may receive commands,control signals, and/or data from the external controller 22 regardingthe parameters of the tests to run. The control processor 38 may thendetermine the control signals and values discussed hereinafter based on,or varying according to, the received parameters.

The control processor 38 may output a first command, control signal,and/or data to the memory controller 30 that determines the delay of thedigital samples due to the coarse delay module 40. The first command,control signal, and/or data may provide the values of the write and readmemory pointers which controls the spacing therebetween, and thuscontrols the timing of the flow of the digital samples through thememory element 28, which sets the value of the delay of the digitalsamples. In the case of a variable delay simulation, control processor38 may change the spacing between the read and write pointers at a rateor frequency (not related to the frequency content of the digitalsamples), f_(update), that can be constant or changing and thereby varythe amount of coarse delay applied to the digital samples by the coarsedelay module 40. The rate or frequency that the spacing between memorypointers changes, f_(update), may be determined and varied according tothe velocity of the target that is being simulated. The maximum value off_(update) is the frequency at which data flows through the memoryelement 28, f_(mem). That is f_(update) ≤ f_(mem).

The control processor 38 may determine configurations of the fractionaldelay filter 32 including the number of stages N, the values of thecoefficients for each filter stage, and the value of the coefficient D.The control processor 38 may also determine a number of samplinginterval divisions, N_(D), based on, or varying according to, a value oramount of fractional delay time to be applied to the digital samples,wherein the time period of each sampling interval division is equal to aminimum value of the fractional delay time coefficient D_(min). Thecoefficient D can be equal to D_(min) × N_(D), wherein N_(D) = ⅟D_(min).In operation, the control processor 38 may determine values for D_(min)and N_(D), and then vary the value of D during the simulation.

The control processor 38 may output a second command, control signal,and/or data to the fractional delay controller 34 that sets a value ofN_(D) and D. The control processor 38 may also update the value of D ata rate, or frequency, less than or equal to a product of the samplinginterval division N_(D) and the flow of digital samples through thememory element 28 f_(mem). That is, f_(update) ≤ N_(D) × f_(mem). If thetest is to involve acceleration or deceleration of the simulated target,then the rate, or frequency, of updating the value of D may vary as afunction of time. The control processor 38 may simulate non-uniformmotion of the target by selecting the value of D from a statisticaldistribution about the nominal value of D that has been computed foreither the constant velocity or non-zero acceleration calculations of D.In such a situation, f_(update) = f_(mem).

The control processor 38 may output a third command, control signal,and/or data to the single sideband modulator 36 that sets or adjusts oneor more values by which the frequency content of the digital samples isincreased or decreased.

In addition, the control processor 38 may receive feedback from thedigital system 12 (through the external configuration block 24). Basedon the feedback, the control processor 38 may adjust the commands,control signals, and/or data communicated to the memory controller 30,the fractional delay controller 34, and the single sideband modulator 36which control the operations of each of these components.

The simulation system 10 may operate as follows. The simulation system10 generally provides a delay of the signal or data from the radarsystem 12, i.e., the digital samples, before the signal or data isreturned to the radar system 12 in order to simulate one or more targetsthat are to be detected by the radar system 12. The delay of the signalor data, which is a period of time between the transmission of thesignal or data from the radar system 12 and the reception of a simulatedreflection of the signal or data by the radar system 12, determines arange, or distance, of the target from the radar system 12 source.Generally, a greater delay of the signal or data corresponds to agreater range of the target, while a smaller delay of the signal or datacorresponds to a smaller range of the target. In addition, a constantdelay of the signal or data may indicate a stationary target, while avariable delay of the signal or data may indicate a moving target.Furthermore, a change in a frequency component of the signal or data mayindicate that the target is moving either toward the radar system 12source or away from it - as would simulate the naturally-occurringDoppler shift of targets moving toward or away from a source.

The radar system 12 outputs the radar output signal, which is receivedby the down conversion circuit 14. The down conversion circuit 14converts the frequency content of the radar output signal from itsnatural frequency value to a lower frequency value and outputs thedown-converted signal. The ADC 16 samples the down-converted signal andgenerates a stream of digital samples.

The memory element 28 of the coarse delay module 40 receives the streamof digital samples from the ADC 16. The memory controller 30 determinesthe locations of the memory element 28 in which the digital samples willbe temporarily stored. The memory controller 30 determines the locationsof the memory element 28 from which the radar samples are read. Thenumber of memory locations or samples between the write location and theread location corresponds to a selectable (determined by the parametersof the test) delay value.

The fractional delay filter 32 of the fine delay module 58 receives thedigital samples as they are read from the memory element 28. Theoperation of the fractional delay filter 32 is determined by, and variesaccording to, the parameters of the type of target simulation to beperformed. If a non-fluctuating, stationary target is to be simulated,then the number of stages N, the values of the coefficients for eachfilter stage, and the value of the coefficient D may be set by thefractional delay controller 34 to provide no fractional delay of thedigital samples. If a fluctuating, or wobbling, stationary target is tobe simulated, then a value of D that dithers around a nominal value maybe chosen. If a moving target is to be simulated, then the number ofstages N, the values of the coefficients for each filter stage, and thevalue of the coefficient D may be set by the fractional delay controller34 to provide fractional delay of the digital samples in order to smooththe motion of the simulated target. The fractional delay may be constantor may be varied (different) for each digital sample. A fluctuatingmoving target, or one with non-uniform motion, may be simulated bydithering the value for the coefficient D around a nominal value. Inaddition, the fractional delay filter 32 may be set up by the fractionaldelay controller 34 to provide simulated micro-Doppler effects(compression of the reflected radar output signal pulse envelope due totarget motion) on the digital samples. The fractional delay controller34 in combination with the fractional delay filter 32 provide finecontrol of the delay of the digital samples - that is, filtering thedata samples to represent delay times that are a fraction of the sampletime period.

The single sideband modulator 36 of the Doppler shift module 60 receivesthe digital samples from the fractional delay filter 32. If no Dopplershift is necessary for the simulation, then the single sidebandmodulator 36 may output the digital samples without any modification. Ifa Doppler shift is needed for the simulation, then the control processor38 may output the necessary commands, control signals, and/or data toinstruct the single sideband modulator 36 to provide the appropriatechange in the frequency content of the digital samples to simulate theDoppler shift. The single sideband modulator 36 outputs the digitalsamples that have been delayed and, optionally, frequency shifted.

The discussion above regarding the coarse delay module 40, the finedelay module 58, and the Doppler shift module 60 describes the exemplaryflow of the digital samples in the sequential order of coarse delaymodule 40, fine delay module 58, and Doppler shift module 60, as shownin FIG. 1 . It is within the scope of the current invention that themodules 40, 58, and 60 may be connected in any sequential order. Forexample, the Doppler shift module 60 may receive the digital samplesfrom the ADC 16. The fine delay module 58 may receive the digitalsamples from the Doppler shift module 60. And the coarse delay module 40may receive the digital samples from the fine delay module 58. Othersequential orders are possible as well. No matter the order of themodules 40, 58, 60, the digital samples that are output by thesimulation system 10 have the appropriate time delay and frequency shiftto simulate the desired targets.

The digital samples are received by the DAC 18 which converts thesamples to the analog intermediate frequency signal. The up conversioncircuit 20 receives the intermediate frequency signal and converts thefrequency content thereof from its natural frequency value to a higherfrequency value. The up conversion circuit 20 outputs the up-convertedsignal, which includes the appropriate amount of coarse delay, finedelay, and Doppler frequency shift to simulate the desired type oftarget. The radar system 12 receives the up-converted signal as theradar input signal and analyzes or processes it to determine what typeof target was simulated. For example, the radar system 12 may determinethat the target was stationary at a certain range (distance). Or theradar system 12 may determine that the target was moving with a certainvelocity and/or at a certain heading. The radar system 12 may outputcommands, signals, and/or data, indicating any information regarding thetarget (determined by the design or application of the radar system 12),as feedback to the external configuration block 24. Depending on thegoal of the test, if the determination of the target type was correct orincorrect, then no changes may occur and the test may conclude or theexternal configuration block 24 may output commands, control signals,and/or data to the control processor 38 to adjust the settings of one ormore of the memory element 28, the fractional delay filter 32, and thesingle sideband modulator 36.

Referring to FIG. 3 , a plot 300 of signal power vs. Doppler frequencyof a signal output by a prior art simulation system. The output signalis similar to the up-converted signal discussed above which would bereceived by the radar system 12 and analyzed for the detection oftargets. The plot 300 illustrates a Doppler spectrum of the outputsignal and includes a peak pulse around the f2 frequency that representsa single target. However, the plot 300 also includes numerous otherlower power level pulses that may be confused for additional targets bythe radar system 12. If it is known that there is supposed to be onlyone simulated target or the target should only have one Dopplerfrequency shift component and the radar system 12 detects multipletargets and / or multiple Doppler frequency shifts, then the test willfail. It may be falsely suspected that the radar system 12 is notfunctioning properly, when it is actually poor quality output from aninferior simulation system.

The simulation system 10 of the current invention corrects for theproblems of the prior art simulation systems. By including at least thefractional delay filter 32 and fractional delay controller 34, thesimulation system 10 outputs a signal that excludes all of the spuriouspulses from the prior art system that may be incorrectly detected astargets. A plot 400 of signal power vs. Doppler frequency for theup-converted signal is shown in FIG. 4 . The plot 400 includes the peakpulse at around the f2 frequency representing the target. But, the restof the plot 400 shows the smooth decay of the signal away from the peakpulse, which results in the radar system 12 properly detecting a singletarget.

A second embodiment of the simulation system 100 is shown in FIG. 5 .The simulation system 100 may include the same modules, a fine delaymodule 102, a Doppler shift module 104, and a coarse delay module 106,as are present in the simulation system 10, but the modules may beformed from different components and may process data in a differentorder. The simulation system 100 could be inserted in the same locationas the simulation system 10 in FIG. 1 to test the operation of the radarsystem 12. The functions of the simulation system 100 may be executed inhardware, software, firmware, or combinations thereof.

The fine delay module 102 generally provides higher resolution controlof the delay of the (radar) data samples. That is, the fine delay module102 may filter the data samples to represent a delay by relativelysmaller delay times, or times that are less than the sample time period.The fine delay module 102 may include a first counter 108, a secondcounter 110, a constant value block 112, a data type converter 114, afirst multiplier 116, a variable time delay unit 118, and a fractionaldelay filter 120.

Input data is received by the fine delay module 102. The input data maybe digital samples received from the ADC 16, or the input data may beretrieved from a data file or generated by a data generator to representdata from the radar system 12. In any case, the input data is a streamof discrete data samples. The data samples are received by the variabletime delay unit 118 which delays the data samples by a delay value thatis set by the first counter 108, which may generate a series of numbersthat increase in value, reset to a start value, and then repeat. Thedata type converter 114 receives the numbers from the first counter 108and converts them to an appropriate format or type to be received by thevariable time delay unit 118. The data samples from the variable timedelay unit 118 are received by the fractional delay filter 120, whichmay be similar in structure and operation to the fractional delay filter32, and may output fine delay data samples. The amount of simulateddelay time filtering provided by the fractional delay filter 120 may bedetermined or set by the second counter 110 which produces a series ofincreasing numbers, similar to the first counter 108. The series ofnumbers are received by the first multiplier 116 which multiplies thenumbers, each number in turn, by a selectable, fractional value,provided by the constant value block 112. The value provided by theconstant value block 112 typically ranges from approximately 0 toapproximately 1 and may be selected or set by an operator prior to, orduring, a simulation of radar targets. The value shown in FIG. 5 ismerely exemplary.

The doppler shift module 104 generally provides a programmable shift infrequency of the (radar) data samples. The doppler shift module 104 mayinclude a first digital delay unit 122, a Hilbert transform unit 124, acosine wave generator 126, a sine wave generator 128, a secondmultiplier 130, a third multiplier 132, and an adder 134.

The fine delay data samples from the fine delay module 102 are receivedby the first digital delay unit 122 and the Hilbert transform unit 124,which convert the samples into in-phase data and quadrature data,respectively. The amount of delay introduced by the first digital delayunit 122 should be roughly equivalent to the amount of delay introducedby the Hilbert transform unit 124. The delay value shown in FIG. 5 ismerely exemplary. The cosine wave generator 126 and the sine wavegenerator 128 also receive doppler shift input data from a source suchas the control processor 38, a data file, or a data generator. Thecosine wave generator 126 may generate cosine wave data, and the sinewave generator 128 may generate sine wave data. The doppler shift inputdata may include frequency and amplitude setting values for the cosineand sine wave data. The cosine wave data and the in-phase data arereceived by the second multiplier 130, and the sine wave data and thequadrature data are received by the third multiplier 132. Eachmultiplier 130, 132 may multiply the data supplied by the inputs and/orperform a frequency mixing function on the input signal data and outputproduct data that includes frequency components which are the sum and/ordifference of the input signal data. That is, the second multiplier 130may output product data that includes frequency components which are thesum and/or difference of the cosine wave data and the in-phase data,while the third multiplier 132 may output product data that includesfrequency components which are the sum and/or difference of the sinewave data and the quadrature data. The adder 134 receives the productdata from the second and third multipliers 130, 132, adds them together,and outputs doppler shift data samples, which are the sum of the twoproduct data streams. The amount of frequency shift in the doppler shiftdata samples is selectable and may include no frequency shift of thefrequency of the fine delay data samples, if that is desired.

The coarse delay module 106 generally provides lower resolution controlof the delay of the (radar) data samples. That is, the coarse delaymodule 106 may delay the data samples by relatively larger delay times,or times that are greater than or equal to the sample time period. Thecoarse delay module 106 includes a second digital delay unit 136. Thesecond digital delay unit 136 receives the doppler shift data samples,delays the samples by a plurality of sample time periods, and outputscoarse delay data samples. Typically, the number of sample time periodsby which the doppler shift data samples are delayed is an integer valueand is selectable. The delay value shown in FIG. 5 is merely exemplary.The coarse delay data samples are communicated to the DAC 18 or storedin a data file to be analyzed to verify the proper operation of thesimulation system 100.

The discussion above regarding the fine delay module 102, the Dopplershift module 104, and the coarse delay module 106 describes theexemplary flow of the digital samples in the sequential order of thefine delay module 102, the Doppler shift module 104, and the coarsedelay module 106, as shown in FIG. 5 . It is within the scope of thecurrent invention that the modules 102, 104, 106 may be connected in anysequential order. For example, the Doppler shift module 104 may receivethe digital samples from the ADC 16. The fine delay module 102 mayreceive the digital samples from the Doppler shift module 104. And thecoarse delay module 106 may receive the digital samples from the finedelay module 102. Other sequential orders are possible as well. Nomatter the order of the modules 102, 104, 106, the digital samples thatare output by the simulation system 100 have the appropriate time delayand frequency shift to simulate the desired targets.

Additional Considerations

Throughout this specification, references to “one embodiment”, “anembodiment”, or “embodiments” mean that the feature or features beingreferred to are included in at least one embodiment of the technology.Separate references to “one embodiment”, “an embodiment”, or“embodiments” in this description do not necessarily refer to the sameembodiment and are also not mutually exclusive unless so stated and/orexcept as will be readily apparent to those skilled in the art from thedescription. For example, a feature, structure, act, etc. described inone embodiment may also be included in other embodiments, but is notnecessarily included. Thus, the current invention can include a varietyof combinations and/or integrations of the embodiments described herein.

Although the present application sets forth a detailed description ofnumerous different embodiments, it should be understood that the legalscope of the description is defined by the words of the claims set forthat the end of this patent and equivalents. The detailed description isto be construed as exemplary only and does not describe every possibleembodiment since describing every possible embodiment would beimpractical. Numerous alternative embodiments may be implemented, usingeither current technology or technology developed after the filing dateof this patent, which would still fall within the scope of the claims.

Throughout this specification, plural instances may implementcomponents, operations, or structures described as a single instance.Although individual operations of one or more methods are illustratedand described as separate operations, one or more of the individualoperations may be performed concurrently, and nothing requires that theoperations be performed in the order illustrated. Structures andfunctionality presented as separate components in example configurationsmay be implemented as a combined structure or component. Similarly,structures and functionality presented as a single component may beimplemented as separate components. These and other variations,modifications, additions, and improvements fall within the scope of thesubject matter herein.

Certain embodiments are described herein as including logic or a numberof routines, subroutines, applications, or instructions. These mayconstitute either software (e.g., code embodied on a machine-readablemedium or in a transmission signal) or hardware. In hardware, theroutines, etc., are tangible units capable of performing certainoperations and may be configured or arranged in a certain manner. Inexample embodiments, one or more computer systems (e.g., a standalone,client or server computer system) or one or more hardware modules of acomputer system (e.g., a processor or a group of processors) may beconfigured by software (e.g., an application or application portion) ascomputer hardware that operates to perform certain operations asdescribed herein.

In various embodiments, computer hardware, such as a processing element,may be implemented as special purpose or as general purpose. Forexample, the processing element may comprise dedicated circuitry orlogic that is permanently configured, such as an application-specificintegrated circuit (ASIC), or indefinitely configured, such as an FPGA,to perform certain operations. The processing element may also compriseprogrammable logic or circuitry (e.g., as encompassed within ageneral-purpose processor or other programmable processor) that istemporarily configured by software to perform certain operations. Itwill be appreciated that the decision to implement the processingelement as special purpose, in dedicated and permanently configuredcircuitry, or as general purpose (e.g., configured by software) may bedriven by cost and time considerations.

Accordingly, the term “processing element” or equivalents should beunderstood to encompass a tangible entity, be that an entity that isphysically constructed, permanently configured (e.g., hardwired), ortemporarily configured (e.g., programmed) to operate in a certain manneror to perform certain operations described herein. Consideringembodiments in which the processing element is temporarily configured(e.g., programmed), each of the processing elements need not beconfigured or instantiated at any one instance in time. For example,where the processing element comprises a general-purpose processorconfigured using software, the general-purpose processor may beconfigured as respective different processing elements at differenttimes. Software may accordingly configure the processing element toconstitute a particular hardware configuration at one instance of timeand to constitute a different hardware configuration at a differentinstance of time.

Computer hardware components, such as communication elements, memoryelements, processing elements, and the like, may provide information to,and receive information from, other computer hardware components.Accordingly, the described computer hardware components may be regardedas being communicatively coupled. Where multiple of such computerhardware components exist contemporaneously, communications may beachieved through signal transmission (e.g., over appropriate circuitsand buses) that connect the computer hardware components. In embodimentsin which multiple computer hardware components are configured orinstantiated at different times, communications between such computerhardware components may be achieved, for example, through the storageand retrieval of information in memory structures to which the multiplecomputer hardware components have access. For example, one computerhardware component may perform an operation and store the output of thatoperation in a memory device to which it is communicatively coupled. Afurther computer hardware component may then, at a later time, accessthe memory device to retrieve and process the stored output. Computerhardware components may also initiate communications with input oroutput devices, and may operate on a resource (e.g., a collection ofinformation).

The various operations of example methods described herein may beperformed, at least partially, by one or more processing elements thatare temporarily configured (e.g., by software) or permanently configuredto perform the relevant operations. Whether temporarily or permanentlyconfigured, such processing elements may constitute processingelement-implemented modules that operate to perform one or moreoperations or functions. The modules referred to herein may, in someexample embodiments, comprise processing element-implemented modules.

Similarly, the methods or routines described herein may be at leastpartially processing element-implemented. For example, at least some ofthe operations of a method may be performed by one or more processingelements or processing element-implemented hardware modules. Theperformance of certain of the operations may be distributed among theone or more processing elements, not only residing within a singlemachine, but deployed across a number of machines. In some exampleembodiments, the processing elements may be located in a single location(e.g., within a home environment, an office environment or as a serverfarm), while in other embodiments the processing elements may bedistributed across a number of locations.

Unless specifically stated otherwise, discussions herein using wordssuch as “processing,” “computing,” “calculating,” “determining,”“presenting,” “displaying,” or the like may refer to actions orprocesses of a machine (e.g., a computer with a processing element andother computer hardware components) that manipulates or transforms datarepresented as physical (e.g., electronic, magnetic, or optical)quantities within one or more memories (e.g., volatile memory,non-volatile memory, or a combination thereof), registers, or othermachine components that receive, store, transmit, or displayinformation.

As used herein, the terms “comprises,” “comprising,” “includes,”“including,” “has,” “having” or any other variation thereof, areintended to cover a non-exclusive inclusion. For example, a process,method, article, or apparatus that comprises a list of elements is notnecessarily limited to only those elements but may include otherelements not expressly listed or inherent to such process, method,article, or apparatus.

The patent claims at the end of this patent application are not intendedto be construed under 35 U.S.C. § 112(f) unless traditionalmeans-plus-function language is expressly recited, such as “means for”or “step for” language being explicitly recited in the claim(s).

Although the technology has been described with reference to theembodiments illustrated in the attached drawing figures, it is notedthat equivalents may be employed and substitutions made herein withoutdeparting from the scope of the technology as recited in the claims.

Having thus described various embodiments of the technology, what isclaimed as new and desired to be protected by Letters Patent includesthe following:

1. A simulation system for use in testing a radar system, the simulationsystem comprising: a coarse delay module configured to receive either afirst stream of digital data samples that are sampled from a radarsignal at a sample time period or a second stream of digital datasamples that are processed by another simulation system component, delaythe digital data samples by a selectable first delay time that isgreater than or equal to the sample time period, and output coarsedelayed samples; a fine delay module configured to receive either thefirst stream of digital data samples or the second stream of digitaldata samples, filter the digital data samples to represent delay by aselectable second delay time that is less than the sample time period,and output fine delayed samples; and a doppler shift module configuredto receive either the first stream of digital data samples or the secondstream of digital data samples, adjust a value of one or more frequencycomponents of the digital data samples, and output doppler shiftedsamples.
 2. The simulation system of claim 1, wherein the coarse delaymodule includes a memory element configured to receive the digital datasamples and store them, each digital data sample stored in a differentone of a plurality of memory locations, the memory element furtherconfigured to transmit the digital data samples, and a memory controllerconfigured to control the operation of the memory element so that thememory element stores each digital data sample for the first delay time.3. The simulation system of claim 2, wherein the memory controller isfurther configured to determine memory locations where the digital datasamples are written to and read from.
 4. The simulation system of claim1, wherein the fine delay module includes a fractional delay filterincluding a plurality of computational stages configured to perform aninterpolation calculation to determine values of the digital datasamples at the second delay time, and a fractional delay controllerconfigured to control the operation of the fractional delay filter bysetting parameters of the computational stages.
 5. The simulation systemof claim 4, wherein the fractional delay filter includes a standalonefilter block configured to receive the digital data samples, filter thedigital data samples, and output filtered data, and each computationalstage includes a first input configured to receive the digital datasamples, a second input receiving an output of an adjacent computationalstage, a filter block receiving the first input, filtering the firstinput, and outputting filtered data, a coefficient block receiving thesecond input, multiplying the second input by a coefficient, andoutputting a product, and an adder adding the filtered data and theproduct and outputting a sum of the filtered data and the product,wherein the second input of the last computational stage receives thefiltered data from the standalone filter block and the output of thefirst computational stage is the output of the fractional delay filter.6. The simulation system of claim 5, wherein the standalone filter blockand the filter block of each computational stage includes a finiteimpulse response filter.
 7. The simulation system of claim 5, whereinthe fractional delay controller determines a number of computationalstages included in the fractional delay filter and a value of thecoefficient of the coefficient block.
 8. The simulation system of claim4, wherein the fractional delay filter includes a Farrow structuredfractional delay filter.
 9. The simulation system of claim 1, whereinthe doppler shift module includes a single sideband modulator configuredto increase or decrease the value of one or more frequency components ofthe digital data samples.
 10. The simulation system of claim 1, whereinthe simulation system receives a feedback signal from the radar systemand adjusts simulation parameters according to a content of the feedbacksignal.
 11. A simulation system for use in testing a radar system, thesimulation system comprising: a coarse delay module configured toreceive either a first stream of digital data samples that are sampledfrom a radar signal at a sample time period or a second stream ofdigital data samples that are processed by another simulation systemcomponent, delay the digital data samples by a selectable first delaytime that is greater than or equal to the sample time period, and outputcoarse delayed samples, the coarse delay module including a memoryelement configured to receive the digital data samples and store them,each digital data sample stored in a different one of a plurality ofmemory locations, the memory element further configured to transmit thedigital data samples, and a memory controller configured to control theoperation of the memory element so that the memory element stores eachdigital data sample for the first delay time; a fine delay moduleconfigured to receive either the first stream of digital data samples orthe second stream of digital data samples, filter the digital datasamples to represent delay by a selectable second delay time that isless than the sample time period, and output fine delayed samples, thefine delay module including a fractional delay filter including aplurality of computational stages configured to perform an interpolationcalculation to determine values of the digital data samples at thesecond delay time, and a fractional delay controller configured tocontrol the operation of the fractional delay filter by settingparameters of the computational stages; and a doppler shift moduleconfigured to receive either the first stream of digital data samples orthe second stream of digital data samples, adjust a value of one or morefrequency components of the digital data samples, and output dopplershifted samples.
 12. The simulation system of claim 11, wherein thefractional delay filter includes a standalone filter block configured toreceive the digital data samples, filter the coarse delayed samples, andoutput filtered data, and each computational stage includes a firstinput configured to receive the digital data samples, a second inputreceiving an output of an adjacent computational stage, a filter blockreceiving the first input, filtering the first input, and outputtingfiltered data, a coefficient block receiving the second input,multiplying the second input by a coefficient, and outputting a product,and an adder adding the filtered data and the product and outputting asum of the filtered data and the product, wherein the second input ofthe last computational stage receives the filtered data from thestandalone filter block and the output of the first computational stageis the output of the fractional delay filter.
 13. The simulation systemof claim 12, wherein the fractional delay controller determines a numberof computational stages included in the fractional delay filter and avalue of the coefficient of the coefficient block.
 14. The simulationsystem of claim 11, wherein the simulation system receives a feedbacksignal from the radar system and adjusts simulation parameters accordingto a content of the feedback signal.
 15. The simulation system of claim11, wherein the fractional delay filter includes a Farrow structuredfractional delay filter.
 16. The simulation system of claim 11, whereinthe doppler shift module includes a single sideband modulator configuredto increase or decrease the value of one or more frequency components ofthe digital data samples.
 17. A simulation system for use in testing aradar system, the simulation system comprising: a fine delay moduleconfigured to receive either a first stream of digital data samples thatare sampled from a radar signal at a sample time period or a secondstream of digital data samples that are processed by another simulationsystem component, the fine delay module including a variable time delayunit configured to receive the digital data samples, delay them by avariable time period, and output variable time delayed samples, and afractional delay filter configured to receive the variable time delayedsamples, filter the variable time delayed samples to represent delay bya selectable first delay time that is less than the sample time period,and output fine delayed samples; a doppler shift module configured toreceive either the first stream of digital data samples or the secondstream of digital data samples, adjust a value of one or more frequencycomponents of the digital data samples, and output doppler shiftedsamples; and a coarse delay module configured to receive either thefirst stream of digital data samples or the second stream of digitaldata samples, delay the digital data samples by a selectable seconddelay time that is greater than or equal to the sample time period, andoutput coarse delayed samples.
 18. The simulation system of claim 17,wherein the fine delay module further includes a first counterconfigured to generate a sequentially increasing first series of numbersthat are communicated to the variable time delay unit to set a delaytime, a second counter configured to generate a sequentially increasingsecond series of numbers, a constant value block configured to generatea numerical value, and a multiplier configured to receive the secondseries of numbers and the numerical value, multiply each number by thenumerical value in turn, and output a product that is communicated tothe fractional delay filter to set a simulated delay time.
 19. Thesimulation system of claim 17, wherein the doppler shift module furtherincludes a hilbert transform unit configured to receive the digital datasamples and output quadrature data, a digital delay unit configured toreceive the digital data samples and output in-phase data with a delayto maintain synchronization of the in-phase and quadrature data streams,a cosine wave generator configured to receive setting data and outputcosine wave data, a sine wave generator configured to receive settingdata and output sine wave data, a first multiplier configured to receivethe cosine wave data and the in-phase data, multiply the cosine wavedata and the in-phase data, and output a first product, a secondmultiplier configured to receive the sine wave data and the quadraturedata, multiply the sine wave data and the quadrature data, and output asecond product, an adder configured to receive the first product and thesecond product, add the first product and the second product, and outputa sum that is the doppler shifted samples.
 20. The simulation system ofclaim 17, wherein the coarse delay module further includes a digitaldelay unit configured to receive the digital data samples, delay themfor a plurality of sample time periods, and output the coarse delayedsamples.